Recently, electronic devices have been downsized, and components have been assembled at high densities into the devices. A conventional clad board for forming circuitry including electronics components mounted thereon has progressed from a single-sided board to a double-sided board, and a multi-layered board is now available. As such, a clad board to include the components at a higher density has been developed in order to accommodate more circuits therein.
Instead of plated through-holes preventing a clad board from accommodating more circuits at a higher density, conductive paste for connections through inner via-holes is proposed (e.g. in Japanese Patent Application Laid-Open No.06-268345).
In this method of manufacturing clad boards, a porous and compressive pre-impregnation sheet (hereinafter called “pre-preg sheet”) including a polymer releasing film on both the faces is used. Through-holes are punched through the pre-preg sheet, and are filled with conductive paste, then the releasing film is peeled off. Metal foils are stuck to both faces of the pre-preg sheet, which is then heated and compressed, whereby both faces become electrically conductive with each other. Then the metal foils are etched for patterning, thereby forming circuits.
This conventional method of manufacturing a clad board will be described hereinafter with reference to accompanying drawings. FIG. 5A through FIG. 5F are sectional views illustrating the conventional method of manufacturing the clad boards.
First, as shown in FIG. 5A, a porous pre-preg sheet 1 of 500 mm square and “t1” mm thickness is prepared. This sheet includes releasing film 2 made of polymer film of approx. 20 um thickness, e.g. polyethylene terephthalate (PET), on both the faces, and a releasing layer made of silicon-based material is formed on one face of film 2. As the porous pre-preg sheet 1, a composite material is employed. The composite material is made of non-woven fabric of aromatic polyamide fiber, in which thermosetting epoxy resin is impregnated.
Next, as shown in FIG. 5B, through-holes 3 are formed at predetermined positions with energy beam such as laser. Pre-preg sheet 1 is placed on a table of a printing machine (not shown) for printing conductive paste 4 onto releasing film 2. Through-holes 3 are filled with paste 4 as shown in FIG. 5C. At this time, upper releasing film 2 prevents a print mask and pre-preg sheet 1 from being contaminated.
As shown in FIG. 5D, films 2 on both the faces of pre-preg sheet 1 are peeled off, then metal foil 5 such as copper foil is stuck to each face of sheet 1 as shown in FIG. 5E. Then sheet 1 is heated and pressed, and metal foil 5 adheres to sheet 1 as shown in FIG. 5F. Simultaneously, sheet 1 is compressed to the thickness of “t2” mm (t1>t2), and the metal foils on both the faces are electrically connected with conductive paste 4. Epoxy resin, one of the components of sheet 1, and conductive paste 4 are cured at this time. Then metal foil 5 on each face is selectively etched for forming circuit patterns (not shown), whereby a double-sided circuit-patterned board is obtained.
However, the method discussed above has the following problems.
Releasing film 2 is stuck to both the faces of pre-preg sheet 1 by the laminating method, as disclosed in Japanese Patent No.2768236. Then, as shown in FIG. 6A and FIG. 6B, at some points in the surface of sheet 1, non-woven fabric 6 is exposed. Even if fabric 6 is not exposed, if large peaks and valleys (roughness) are formed on a face of a surface resin layer, sheet 1 does not securely adhere to film 2. Yet, fine gaps 10 are formed on the interface between sheet 1 and film 2, as shown in FIG. 7A and FIG. 7B.
When through-holes 3 of such pre-preg sheet 1 are filled with conductive paste 4, particularly when through-hole 3 is provided at gap 10, conductive paste 4 also penetrates into gap 10 as shown in FIG. 7C. As a result, a pattern touches an adjacent pattern while the circuits are formed, which produces a short-circuit or lowers insulating reliability between wiring. These problems increases at a higher density of wiring patterns.